10, Automatyka i Robotyka, Semestr IV, Technika Cyfrowa, TC, Technika Cyfrowa, Laboratoria, Lab4
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// ULFIG MATEUSZ// PAWEL ZYDZIAK`timescale 1ns / 1psmodule gumis(E,clk,x,y);input clk;input E;output reg x = 0;output reg y = 0;reg [25:0]i=0;wire clk2;IBUFG a(.I(clk),.O(clk2));always @ (posedge clk2)beginif (E==1)begini<=i+1;if(i==(26'h2000000))beginx<=1;i<=0;y<=~y;endelsebeginx<=0;endendendendmodule/////////////////////////////////////////////////////////// ZAD 2 ////////////////////////////////////////////////////////////////////////////////`timescale 1ns / 1psmodule gumis2(clk, x0, x1, cin, cout);input [1:0]x,cin,clk;output reg cout;reg [2:0]temp=0;always@(cin)begintemp=temp+1;endalways@(temp)begincase(x)'b00:beginif (temp==0) begincout<=1;end elsebegincout<=0;temp<=0;end'b01:beginif (temp==0) begincout<=1;end else beginif (temp==1) begin cout<=0; endend elsebegin cout<=0;temp=0;end'b10:beginif (temp==0) begincout<=1;endelsebeginif (temp==1) begin cout<=0; endelse beginif(temp==2)begin cout<=0;end else begincout<=0;temp<=0;endendend'b11:beginif (temp==0) begincout<=1;endelsebeginif (temp==1) begin cout<=0; endelse beginif(temp==2)begin cout<=0;end else begin if (temp==3)begincout<=0;endelse begintemp<=0;cout<=0;endendendendendendendendendendmodule
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